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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:14:30 02/29/2012 
-- Design Name: 
-- Module Name:    RegistroIR - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity RegistroIR is
    Port ( ins_word_in : in  STD_LOGIC_VECTOR (17 downto 0);
           reset : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           loadEnable : in  STD_LOGIC;
           IR_OUT : out  STD_LOGIC_VECTOR (17 downto 0));
end RegistroIR;

architecture Behavioral of RegistroIR is

begin
	process (clk) begin

			if (reset = '1') then
				IR_OUT <= ext ("0", 18);
			elsif (loadEnable = '1') then
				IR_OUT <= ins_word_in;
			end if;

	end process;
end Behavioral;

